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We discover a number of low-power design methods that I typically see ignored however that may make a giant distinction.
Designing an embedded system for battery life has change into an vital design consideration for a lot of groups. The flexibility to optimize battery life will help to lower in-field upkeep prices and be sure that clients have a great expertise with the product by not having to vary or cost batteries repeatedly.
There are fairly a number of normal methods that groups use to assist enhance battery life. For instance, placing the processor into low energy modes, turning off unused peripherals, and many others. Nevertheless, I’ve discovered that growth groups typically overlook some normal methods.
In as we speak’s submit, we are going to discover a number of low-power design methods that I typically see ignored however that may make a giant distinction.
Method #1 – Ditch GCC for a industrial compiler
As software program builders and groups, we’ve grown complacent with utilizing free and open-source instruments. We frequently neglect that, most often, you get what you pay for. Whereas GCC is a incredible software, it isn’t appropriate in all circumstances. A type of situations is for low-power, battery-operated units.
I not too long ago did some efficiency measurements to check code execution between GCC and IAR’s EWARM compiler. Compiling the identical code for a similar processor with similar settings resulted in a 20 – 30% enchancment in efficiency for the take a look at code. Outcomes diverse based mostly on the operations, however these numbers are staggering.
What does it imply? Which means with a industrial compiler, you might be able to execute the identical code far sooner, which suggests you may get again to sleep mode sooner. Extra time spent in sleep mode means much less present draw and a better chance of the battery lasting longer!
Utilizing a industrial compiler could also be some low-hanging fruit you possibly can make the most of to get not simply higher efficiency out of your code but additionally a method to save battery life.
Observe: The consequence will fluctuate based mostly on how good you might be at hand optimizing code. However why waste all that point when the software can do it for you?
Method #2 – Use Tickless mode to remain asleep longer
An issue with low-power modes is that if you happen to use an RTOS, the kernel tick will periodically get up the system. It’s not unusual for the tick to be set at one millisecond. What occurs if you’d like your gadget to sleep for a full minute earlier than waking up? Nicely, you’ll get up 6,000 extra instances throughout that minute than you’d like, wasting your battery life.
One simple resolution in lots of RTOSes is to make use of tickless mode. The concept behind the mode is that when the system goes to sleep, it scales a low-power timer in order that the RTOS tick doesn’t happen each millisecond. As a substitute, it could not occur for minutes, hours, or perhaps a day!
As you possibly can think about, this retains the system asleep and prevents it from waking up and operating a bunch of pointless CPU cycles. The result’s much less present used, equating to longer battery life.
Observe: The strategy for enabling tickless mode and the work it’s possible you’ll have to put in as a developer varies from one RTOS to the following.
Method #3 – Leverage the interior cache
For years, microcontrollers didn’t have a cache. They had been resource-constrained units that had been comparatively easy in comparison with their extra feature-rich older siblings. That isn’t the case as we speak. In the event you take a look at microcontroller components from ST, NXP, and plenty of others, you’ll discover that the efficiency components all have an inside cache. In case you are designing for low energy, you possibly can leverage the cache to enhance vitality consumption.
A number of mechanisms permit the cache that can assist you lower present consumption. Most relate to the cache’s major perform: to supply sooner entry to regularly used information or directions, thereby decreasing the CPU’s time spent accessing slower important reminiscence.
For instance, you need to use the cache to optimize reminiscence entry patterns. A cache can considerably optimize vitality use in functions with predictable reminiscence entry patterns. By successfully prefetching and caching the required information and directions, the microcontroller minimizes the energy-expensive accesses to the principle reminiscence.
The cache supplies decrease latency and better pace entry than different onboard reminiscence. The result’s that much less time is spent on reminiscence accesses, which permits the CPU to have fewer idle cycles. Quicker entry additionally means the CPU can end the duty sooner, lowering the general lively CPU time. All these items assist to scale back the processor’s general vitality consumption, leading to longer-lasting battery life.
Conclusions
When builders and groups take a look at low-power design, they typically leap straight to sleep modes, clock gating, and different methods to lower vitality consumption. Whereas these are all nice methods, they often overlook the straightforward methods which can be additionally low-hanging fruit. We’ve checked out a number of on this submit that you need to use to assist enhance your gadget’s battery life or lower the vitality consumption of your powered gadget.
Finally, there’s a lot that goes right into a low-power design. You’ll be able to optimize for vitality indefinitely, however there’s typically a “knee” within the optimization course of that can lead to fewer features in battery life for the hassle. All the time hold observe of how your methods enhance your battery life; if you hit that knee, it’s time to cease optimizing!
Jacob Beningo is an embedded software program marketing consultant who makes a speciality of real-time, microcontroller-based programs. He actively promotes software program greatest practices by quite a few articles, blogs, and webinars on subjects from software program structure design, embedded DevOps, and implementation methods. Jacob has 20 years of expertise within the discipline and holds three levels together with a Masters of Engineering from the College of Michigan.
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