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Normal goal input-output (GPIO) pins are the best peripherals.
The hyperlink to an object underneath management (OUC) could turn into inadvertently unreliable as a consequence of many causes: a lack of contact, brief circuit, temperature stress or a vapor condensate on the parts. Typically a greater hyperlink might be established with the favored bridge chip by merely exploring the probabilities supplied by the chip itself.
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
The bridge, corresponding to NXP’s SC18IM700, normally gives a specific amount of GPIOs, that are useful to implement a check. These GPIOs protect all their performance and can be utilized as ordinary after the check.
03.18.2024
03.18.2024
03.18.2024
To make the check potential, the chip will need to have multiple GPIO. This fashion, they are often paired, bringing the chance for the members of the pair to ballot one another.
For the reason that exercise of the GPIO throughout check could hurt the common features of the OUC, one of many GPIO pins might be chosen to short-term prohibit these features. Fairly often, when this object is sort of inertial, this prohibition could also be omitted.
Determine 1 exhibits how the thought might be applied within the case of the SC18IM700 UART-I2C bridge.
Determine 1: Self-testing GPIO utilizing the SC18IM70pytho0 UART-I2C bridge.
The values of resistors R1…R4 have to be massive sufficient to not result in an unacceptably massive present; alternatively, they need to present adequate voltage for the logic “1” on the enter. The values proven on Determine 1 are good for probably the most purposes however could must be adjusted.
Some difficulties could come up solely with a quasi-bidirectional output configuration, since on this configuration it’s weakly pushed when the port outputs a logic HIGH. The issue could happen when the resistance of the corresponding OUC enter is simply too low.
If the info charge of the UART output is simply too excessive for a correct charging of the OUC-related capacitance throughout the check, it may be decreased or, the corresponding values of the resistors might be lessened.
The sketch of the Python subroutine follows:
PortConf1=0x02
PortConf2=0x03
def selfTest():
knowledge=0b10011001
bridge.writeRegister(PortConf1, knowledge) #PortConfig1
knowledge=0b10100101
bridge.writeRegister(PortConf2, knowledge) #PortConfig2
#— write 1
cc=0b11001100
bridge.writeGPIO(cc)
aa=bridge.readGPIO() # 0b11111111
if aa != 0b11111111 : return False # verify
#—- write 0
cc=0b00000000
bridge.writeGPIO(cc)
aa=bridge.readGPIO()
if aa != 0b00000000 : return False # verify
# companions swap
knowledge=0b01100110
bridge.writeRegister(PortConf1, knowledge) #PortConfig1
knowledge=0b01011010
bridge.writeRegister(PortConf2, knowledge) #PortConfig2
#—write 1
cc=0b00110011
bridge.writeGPIO(cc)
aa=bridge.readGPIO()
if aa != 0b11111111 : return False # verify
#—- write 0
cc=0b00000000
bridge.writeGPIO(cc)
aa=bridge.readGPIO()
if aa != 0b00000000 : return False # verify
# verify quasy-bidirect
knowledge=0b01000100
bridge.writeRegister(PortConf1, knowledge) #PortConfig1
knowledge=0b01010000
bridge.writeRegister(PortConf2, knowledge) #PortConfig2
#—write 1
cc=0b00110011
bridge.writeGPIO(cc)
aa=bridge.readGPIO()
if aa != 0b11111111 : return False # verify
#—- write 0
cc=0b00000000
bridge.writeGPIO(cc)
aa=bridge.readGPIO()
if aa != 0b00000000 : return False # verify
return True
—Peter Demchenko studied math on the College of Vilnius and has labored in software program improvement.
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