[ad_1]
Alphawave Semi introduced the profitable bring-up of its first chiplet-connectivity silicon platform on TSMC’s superior 3-nm course of. The silicon-proven Common Chiplet Interconnect Specific (UCIe) subsystem, able to working at 24 Gbps per lane, was demonstrated on the latest Chiplet Summit in Santa Clara, CA.
Combining PHY IP and interface controller IP, the UCIe 1.1-compliant subsystem delivers excessive bandwidth density at very low energy and with low latency. Its configurable die-to-die (D2D) controller helps streaming, PCIe/CXL, AXI-4, AXI-S, CXS, and CHI protocols. As well as, the PHY might be configured for TSMC’s chip-on-wafer-on-substrate (CoWoS) and built-in fanout (InFO) packaging applied sciences. Constructed-in bit error fee (BER) well being monitoring ensures dependable operation.
“Attaining 3nm silicon-proven standing for our 24-Gbps UCIe subsystem is a key milestone for Alphawave Semi, as it’s a necessary piece of our chiplet connectivity platform tailor-made for hyperscaler and data-infrastructure functions,” stated Letizia Giuliano, VP IP Product Advertising and marketing at Alphawave Semi. “We’re grateful to our TSMC group for his or her excellent help, and we look ahead to accelerating our mutual prospects’ high-performance chiplet-based designs on TSMC’s modern 3nm course of.”
03.12.2024
03.11.2024
03.08.2024
Learn extra in regards to the UCIe subsystem on Alphawave Semi’s weblog.
Discover extra datasheets on merchandise like this one at Datasheets.com, searchable by class, half #, description, producer, and extra.
[ad_2]
Supply hyperlink
