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Among the commentary in response to Half 1 on this subject recommended that the 2 1 pF capacitors, C4 and C5, needed to be put in sequence for lack of availability of 0.5 pF elements.
A simulation of that introduced circuit is seen as follows:
Determine 1 The circuit with a floating node and its Bode plot simulation.
Half picks differ considerably from the unique. These op-amps are digital, the JFET is merely an out there half from the simulation software program and the diode represents the unique photodiode. For all of that, these are all shut sufficient. Please notice the Bode plot of this configuration.
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To maintain utilizing the pair of 1 pF capacitors, the next schematic is identical as above however with the addition of another resistor, R8, in parallel with C4.
Determine 2 The circuit and not using a floating node (an extra resistor R8 added in parallel with C4) and its Bode plot simulation.
At 10 MΩ, resistor R8 gives a DC path for the previously floating node to maintain that node’s voltage from unpredictably shifting. Observe that the Bode plot for this modified circuit is indistinguishable from the plot seen earlier than.
Different choices for tethering the previously floating node exist as properly. For instance, R8 may very well be tied from the C4 and C5 junction to floor, once more, with no seen impact on the Bode plot.
Your best option is greatest left to the designer.
John Dunn is an electronics guide, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York College (MSEE).
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