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At this yr’s Synopsys Consumer Group (SNUG) convention in Santa Clara, California, Synopsys CEO each introduced a lot of new instruments and initiatives in addition to demonstration of traction of its AI-driven EDA instruments.
The corporate highlighted the market momentum for its Synopsys.ai suite which incorporates the DSO.ai and VSO.ai instruments, and launched the 3DSO.ai instrument to allow 3D design house optimization for rising multi-die programs and architectural exploration with new two new hardware-assisted verification (HAV) options for quicker, larger capability emulation and prototyping. A brand new Cloud Hybrid resolution was additionally introduced, geared toward addressing a big hurdle for mid-large semiconductor clients which have on-prem information facilities however are typically restricted by capability.
In his keynote speech on the convention, Synopsys CEO Sassine Ghazi stated, “The speedy development of AI, silicon proliferation, and software-defined programs are driving the period of pervasive intelligence, the place know-how is seamlessly built-in into our lives, bringing with it unprecedented alternative and better compute, power, and design challenges for the know-how {industry}.”
Ghazi stated Synopsys.ai has achieved a whole bunch of tape-outs to this point and is delivering ‘beautiful’ buyer outcomes. (Picture: Synopsys)
Ghazi stated Synopsys.ai has achieved a whole bunch of tape-outs to this point and is delivering ‘beautiful’ buyer outcomes. (Picture: Synopsys)
Ghazi stated Synopsys.ai has achieved a whole bunch of tape-outs to this point and is delivering ‘beautiful’ buyer outcomes. (Picture: Synopsys)
Sassine Ghazi (proper). (Picture: Nitin Dahad)
Ghazi stated Synopsys.ai has achieved a whole bunch of tape-outs to this point and is delivering beautiful buyer outcomes together with a greater than 10% enhance in efficiency, energy, space (PPA), as much as 10X quicker turn-around time and double-digit enhancements in verification protection, 4X quicker check with the identical protection, and 4x quicker analog circuit optimization when in comparison with optimization with out the usage of AI.
You possibly can watch my video interview with Ghazi right here, wherein he additionally talks about Synopsys’ acquisition of SRAM PUF safety IP agency Intrinsic ID, additionally introduced on the convention. I additionally talked to Ravi Subramaniam, normal supervisor of the programs design group at Synopsys, to elucidate extra concerning the virtualization of chip design, the altering nature of shoppers (e.g. Tesla), and the way Synopsys instruments—coupled with the acquisition of PikeTec final yr and now Ansys—builds out the corporate’s skill to ship the instruments wanted to cope with the interaction of {hardware} and software program co-design for advanced units.
You possibly can watch my video interview with Subramaniam under:
Multi-die exploration with 3DSO.ai
As a part of its efforts to drive mainstream adoption of multi-die designs, Synopsys launched 3DSO.ai, a brand new AI-driven functionality delivering what it stated is ‘unparalleled productiveness positive factors’ whereas maximizing system efficiency and high quality of outcomes. Constructed natively into Synopsys 3DIC compiler, a unified exploration-to-signoff platform, and powered by quick built-in evaluation engines, 3DSO.ai gives optimization for sign integrity, thermal integrity, and power-network design. Synopsys 3DSO.ai is now accessible to early adopters.
In his keynote, Ghazi highlighted Synopsys’ industry-first resolution for early structure exploration of multi-die programs, Synopsys Platform Architect – Multi-Die. He stated that this platform accelerates design timelines, delivering a dramatic 6-12 month “shift left” from RTL for the evaluation of efficiency and energy, whereas accounting for the interdependencies between a number of dies. It permits programs architects to automate modeling, simulation, and evaluation for early partitioning choices, and helps clients keep away from expensive, late-stage adjustments and re-spins.
Moreover, he emphasised the significance of multi-die options, spotlighting Intel’s Pike Creek, the world’s first silicon-proven UCIe-connected and a results of collaboration between Intel, TSMC and Synopsys. The chip, a collaboration between Intel, TSMC and Synopsys, consists of an Intel UCIe IP die constructed on its Intel 3 course of node and a Synopsys UCIe IP die constructed on the TSMC N3E course of. Ghazi commented, “That is the way forward for the semiconductor {industry}: a number of fabs, a number of units of {industry} customary UCIe IP, and fashionable EDA packaging options.”
New {hardware} assisted verification options
Throughout his keynote, Ghazi defined that as AI turns into pervasive, software program performs a a lot bigger position in semiconductor design, demanding a holistic programs method to silicon innovation. From massive, monolithic SoCs for AI workloads to new multi-die programs, the complexity and software-defined nature of immediately’s designs requires verification programs with larger efficiency and better capability. On this context, Synopsys unveiled two new hardware-assisted verification (HAV) options for quicker, larger capability emulation and prototyping.
Synopsys ZeBu EP2 is the newest model within the Synopsys ZeBu EP household of unified emulation and prototyping programs. Accessible now, the brand new system gives the quickest emulation and prototyping platform for AI workloads, making it excellent for software program bring-up, software program/{hardware} validation, and energy/efficiency evaluation.
After which the Synopsys HAPS-100 12 system is Synopsys’ highest capability and density FPGA-based prototyping system, with a mixture of fastened and versatile interconnects and a rack-friendly design, significantly helpful for prototyping large designs that require many FPGAs, equivalent to multi-die programs and huge SoCs. Accessible now, this new prototyping system shares a standard {hardware} platform with Synopsys ZeBu EP2.
Collectively, these new choices develop the {industry}’s broadest HAV portfolio, serving to clients cut back design dangers and be sure that more and more advanced semiconductor designs carry out as meant.
Hybrid cloud supply for bursting and enhanced engineering productiveness
One other announcement at SNUG was the launch of Synopsys Cloud Hybrid resolution, which the corporate stated addresses a big hurdle for mid-large semiconductor clients which have on-prem information facilities however are typically restricted by capability and constrained on time. The brand new hybrid cloud resolution permits these clients to seamlessly and effectively burst from on-prem information facilities to the cloud throughout peak wants.
Synopsys’ new hybrid cloud resolution permits clients to seamlessly and effectively burst from on-prem information facilities to the cloud throughout peak wants. (Picture: Synopsys)
Synopsys’ new hybrid cloud resolution permits clients to seamlessly and effectively burst from on-prem information facilities to the cloud throughout peak wants. (Picture: Synopsys)
Synopsys’ new hybrid cloud resolution permits clients to seamlessly and effectively burst from on-prem information facilities to the cloud throughout peak wants. (Picture: Synopsys)
As well as, it takes important handbook effort to designate sure blocks for on-prem sources and the cloud, plus further time to switch related design information and sync the information units for processing. Synopsys Cloud Hybrid mechanically splits the job based mostly on accessible capability and gives automated real-time information synchronization between a buyer’s cloud surroundings and on-prem information middle. The answer eliminates the necessity for time-consuming, handbook information transfers, serving to clients maximize engineering productiveness and speed up time to outcomes.
Synopsys Cloud Hybrid Resolution is out there to early entry clients with a Synopsys Cloud contract.
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